Forum Post: RE: AXI channel handshake process
It is there to avoid a deadlock on the channel. If the source waits for READY assertion before asserting VALID, and the destination waits for VALID assertion before asserting READY, nothing will...
View ArticleForum Post: AXI Read Transaction Dependencies
What if RVALID is asserted before the ARVALID and ARREADY, and also RREADY has been already asserted?
View ArticleForum Post: AXI3 write response dependencies
Write Transaction dependencies define that WVALID and WREADY, both are asserted then BVALID can be asserted. So the issue can be raised there that what if AWVALID and AWREADY, both are deasserted...
View ArticleForum Post: Output Compare not working for STM32F407 Discovery Board
Hi, I am working on STM32F407 Discovery board. I am trying to use output compare mode in stm32 for led toggle. Here is the code I have written #include "stm32f4xx.h" //Header File for STM32F4 device...
View ArticleForum Post: RE: Debugging a Cortex-M0 Hard Fault
I have here invalid value to LR when any normal ISR was happened. how can I know LR Value in this case to get the previous code line which was executed before this interrupt. and why in call stack...
View ArticleForum Post: SWD stopped working after write to core registers
Hi. I have a task - make a simple implementaton of SWD protocol, that will be used to program one STM32F4 throught another one. For that purpose, host STM uses pins of PORTD, target is connected with...
View ArticleForum Post: how to get Link Register when it has 0xFFFFFFF9 in ISR
I have here invalid value to LR when any normal ISR was happened. every Isr get the same behavior. how can I know LR Value in this case to get the previous code line which was executed before this...
View ArticleForum Post: RE: AXI Read Transaction Dependencies
Simple, it's a protocol violation. " The slave must wait for both ARVALID and ARREADY to be asserted before it asserts RVALID to indicate that valid data is available. " A slave doesn't know what read...
View ArticleForum Post: RE: AXI3 write response dependencies
The issue here with AXI3 is that a slave could return a B channel write response without knowing what the AW channel write request actually was (AWVALID or AWREADY, or both still deasserted). This was...
View ArticleForum Post: AXI4:- Unaligned transfer
While doing an unaligned transfer of 32-bit data on 64-bit data, using 0x001 address, lower address lines used to indicate an unaligned data transfer but what if this lower address line data also needs...
View ArticleForum Post: NIC301 sizing
Hi ARM experts, I am configuring a network in which data width of busmatrix is 32bit and data with of slave is 64bit. In write transaction, high half and low half of wstrb_slave[7:0] toggles...
View ArticleForum Post: Is routerlogin net not working properly?
Try to access the routerlogin net or routerlogin.com URL in your browser and it shows an error "You are not connected to your router's WiFi Network". Then you can try to access the Netgear router login...
View ArticleForum Post: RE: NIC301 sizing
I think for this sort of question you would need to email the ARM support addresses your company should have access to if it has license the PL301 directly from them. If you have not licensed this IP...
View ArticleForum Post: RE: AXI4:- Unaligned transfer
The big question here is what is AWBURST signalling ? If AWBURST indicates an INCR burst, the 4 transfers in your example would be to 0x001 (3 bytes) using WDATA[31:8], then 0x004 (4 bytes) on...
View ArticleForum Post: RE: AXI4:- Unaligned transfer
how only 3 bytes are transferred in first transfer in INCR type burst, not whole 32-bits?
View ArticleForum Post: AXI3 WRAP burst
what is a sound reason to choose the only start_address that is aligned to the size of each transfer?
View ArticleForum Post: About AXI protocol Specification
Under the section of "About the AXI protocol" specification states that AXI Protocol "meets the interface requirement of the wide range of component" please elaborate in a wider sense?
View ArticleForum Post: RE: AXI3 WRAP burst
I'm not sure if you are asking why WRAP burst transfers need to use AxSIZE aligned addresses, or why you might use a WRAP burst that doesn't actually wrap because it starts at the wrap boundary. So to...
View ArticleForum Post: RE: AXI4:- Unaligned transfer
Because you used an unaligned start address. The AXI protocol works best with aligned transfers, so by using an unaligned address you restrict the amount of data in an aligned range that you can...
View ArticleBlog Post: Docker enables Arm Cycle Model Studio on Ubuntu
Arm Cycle Model Studio (CMS) is a useful tool to create SystemC simulation models from Verilog RTL source code. SystemC models that are created with CMS run well with a variety of simulators and are...
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